The present invention relates in general to the field of semiconductor device fabrication and, more particularly, to a system for optimizing the manufacture of short gate lengths.
Manufacturing cost of an integrated circuit is largely dependent upon the chip area required to implement desired functions. A chip area is defined by the geometries and sizes of active components disposed on a wafer substrate. Active components include gate electrodes in metal-oxide semiconductors (MOS), and diffused regions such as MOS source and drain regions, and bipolar emitters, collectors and base regions. The geometries and sizes of these features are often dependent upon the photolithographic resolution available for the particular equipment used in processing the integrated circuit.
Photolithography typically relies on a mask and a light source to expose and pattern an underlying photoresist layer for use with, e.g., etching steps. The photoresist may be either a positive or negative photoresist. After exposure, the exposed (positive) or unexposed (negative) portions of the photoresist are removed leaving a patterned layer of photoresist for the next process step. When forming minute patterns, for ultra large scale integration (ULSI) devices, a projection and reduction exposure method is typically used. Projection and reduction is useful for ULSI as very small patterns can be resolved because mask precision is also reduced.
A significant problem of conventional photolithographic techniques as applied to ULSI, as more and more layers are added, is that additional steps add additional complexity to the creation of circuits on the wafer surface. The resolution of small image sizes in photolithography becomes more difficult due to light reflection and the thinning of the photoresist during processing.
As a two dimensional process used to achieve a three dimensional structure, the goal of photolithographic patterning is to establish the horizontal and vertical dimensions of the various devices and circuits used to create a pattern that meets design requirementsxe2x80x94such as correct alignment of circuit patterns on the wafer surface. As line widths shrink, photolithography of patterns down to the nanometer level, and smaller, approach the limits of resolution of present equipment. These sub-nanometer line widths become increasingly more difficult to pattern because of the limits of the wavelength of light used for exposure.
The present invention recognizes the need for reduced polysilicon gate line-end loss in ULSI integrated circuits. As gate surface areas and spacing are reduced, so are margins between adjacent devices. Spacing problems are further accentuated at the end of lines created using conventional and phase shift photolithography, due to light scatter at the line-end corners. Also, techniques to reduce gate length tend to increase line-end loss. In order to permit devices to be closer together, the spacing between lines must be reduced. Line-end loss increases final spacing between lines, limiting reductions in spacing between devices.
Current use of alternate phase shift photolithography attempts to reduce gate length by using two phase shift patterns (0 and 180 degree) in the gate regions. A second exposure is used to define other regions, including line-ends.
The present invention uses two photolithographic masks. However, the two masks of the present invention are optimized to reduce gate length (width of the patterned line), while also decreasing line-end loss.
More particularly, the present invention provides for producing a gate on a substrate, wherein a first mask is used to pattern the width of the polysilicon and a second mask is used to pattern the line-end cuts prior to polysilicon etching. The present invention results in a significant decrease in the line-end loss critical to maintaining the dimensions of the polysilicon. Thus, the system of the present invention provides a reduction in end loss and device variation, with the same number of processing steps and with the attendant increase in efficiency and yield.
The present invention optimizes the line-ends by, e.g., reducing the corner rounding and line-end pull back caused by scattered light, and by separate optimization of the spacing and the width of the exposure. The present invention provides both high reliability and high performance. The masks created for the present invention may be formed consistently using existing process equipment, processes and workflows. The first and second masks may also be used with existing techniques and materials without the need to implement new processes or upgrade current equipment.